This is an asynchronous temporal relation for which the nth tick of the left clock occurs before the nth tick of the right clock. In short, the left clock is faster than the right clock.

Example of a CCSL specification:

 * c1 precedes c2
 * @author: Julien DeAntoni
 * date : Wed jul 8th 2011

ClockConstraintSystem  MySpec {
    imports {
        import "ccsl:kernel" as kernelLib ; //add the kernel constraints to your specification
    entryBlock main

    Block main {

            Clock c1
            Clock c2
            Relation r1[Precedes](LeftClock -> c1, RightClock -> c2 )


Simulation results:

a Precedes simulation


on the top, the timing diagram (VCD) where the pulses represent the ticks of clocks.

The horizontal sequence represents the logical time increase.

On the left bottom, the constraint that can be represented on the timing diagram; the next picture shows the representation of the relation between the instants in this diagram. While the simulation is computed as a total order, the instant relations computed during the simulation (and represented on the next picture) provide one of the partial orders that are acceptable solutions of the specification.

Finally, on the bottom right, the clock domains are represented; here the two clocks are linked by an asynchronous relation: precedes. In the other examples, you could see the subclock / equality or exclusion relations.

a Precedes partially ordered solutiuon (with instant relations)