This is a synchronous temporal expression. It creates an implicit clock that is the result of the expression. The implicit clock ticks only once after a specific number of  ticks of the clock provided as a parameter. After its unique tick, the implicit clock dies (it cannot tick anymore). To ease the reading we have added a coincidence relation between the implicit result clock and an explicit clock named c2.

the CCSL specification:

 * c3 = c1 wait 5
 * @author: Julien DeAntoni
 * date : Mon july 18th 2011

ClockConstraintSystem  MySpec {
    imports {
        import "ccsl:kernel" as kernelLib ; //add the kernel constraints to your specification
    entryBlock main

    Block main {

            Clock c1
            Clock c2

            Integer delay = 5
            Expression c1wait5 = Wait(
WaitingClock -> c1, WaitingValue -> delay)
            Relation r1[Coincides](Clock1 -> c2, Clock2 -> c1wait5 )


Simulation results:

The Wait expression simulation is represented on the next picture. On important point is that after its sole tick, the implicit clock dies (represented by a yellow line on the picture). Because c2 is coincident with the implicit clock, then it dies at the same time than the implicit clock.

On the bottom right side, the clock domain is represented; here, the resulting clock is a subclock of the clock provided as parameter

a wait expression simulation