This is a synchronous temporal relation for which the nth tick of the left clock appears simultaneously with the nth tick of the right clock.

Example of CCSL specification:

 * c1 coincides with c2
 * @author: Julien DeAntoni
 * date : Wed jul 8th 2011

ClockConstraintSystem  MySpec {
    imports {
        import "ccsl:kernel" as kernelLib ; //add the kernel constraints to your specification
    entryBlock main

    Block main {

            Clock c1
            Clock c2
            Relation r1[Coincides](Clock1 -> c1, Clock2 -> c2 )


Simulation results:

a Precedes simulation


on the top, the timing diagram (VCD) where the pulses represent the ticks of a clock.

The horizontal axis represents the logical time increase.

On the left bottom, the constraint that can be represented on the timing diagram; the next picture shows the representation of the relation between the instants in this diagram. While the simulation is computed as a total order, the instant relation computed during the simulation (and represented on the next picture) provides one of the partial orderings that is an acceptable solution for the specification. Of course, with only a single constraint (coincides) the solution is unique and the order is total.

Finally, on the bottom right, the clock domains are represented; here the two clocks are linked by a synchronous relation: ==. Note that it does not mean that objects are equals; each clock has its own identity but the equality in time: they always tick simultaneously.

a Precedes partially ordered solutiuon (with instant relations)