Defer:

This is a mixed temporal expression. Like any expression, it creates an implicit clock that is the result of the expression. To understand how it works, the reader must think about its personnal calendar. The expression takes a sequence as a parameter. A sequence has a finite part and a infinite part (the one between the parenthesis).

Each time the 'BaseClock' *(i.e., c1 in the example)* ticks, a meeting for the next 'n' ticks of the 'DelayClock' *(i.e., c2)* is taken. where 'n' is the current number in the sequence.

If the sequence has an empty infinite part, the implicit clock dies after its last tick.To ease the reading we have added a coincidence relation between the implicit result clock and an explicit clock named res.

The first CCSL specification (with an infinite part):

/*

* res = c1 defer by 1; 3 ( 6 )

* @author: Julien DeAntoni

* date : Mon july 18th 2011

*/

ClockConstraintSystem MySpec {

imports {

**import** "ccsl:kernel" as kernelLib ; //add the kernel constraints to your specification

}

entryBlock main

Block main {

**Clock c1**

**Clock c2**

**Clock res**

Sequence s1 : IntegerSequence =

un = 1;

six = 6

(trois = 3)

**Expression** myDefer = **Defer**( BaseClock -> **c1**, DelayClock -> **c2**, DelayPatternExpression -> s1)

** Relation** r1[**Coincides**](Clock1 -> **c3**, Clock2 -> myDefer )

}

}

Simulation results:

On the picture below, the first tick of clock c1 schedules a tick of the result after one tick of c2. The second tick of c1 schedules a tick of the result after 6 ticks of c2. Finally, all other ticks of c1 schedule a tick of the result after 3 ticks of c2. On the picture, we can see that the third tick of c1 has caused the second tick of the result while the second tick of c1 has caused the third tick of the result. When two ticks are scheduled at the same tick, everything is like if only one were scheduled. This is exactly like sometimes in your calendar, you have meetings which are scheduled from a long time and some others are added just before the actual date.

On the bottom right, the clock domain is represented; here, the resulting clocks is a subclock of the 'DelayClock' *(i.e., c2)* and the 'BaseClock' *(i.e., c1)** *precedes the implicit clock.

the second CCSL specification (with an empty infinite part):

/*

* res = c1 defer by 1; 3 ( 6 )

* @author: Julien DeAntoni

* date : Mon july 18th 2011

*/

ClockConstraintSystem MySpec {

imports {

**import** "ccsl:kernel" as kernelLib ; //add the kernel constraints to your specification

}

entryBlock main

Block main {

**Clock c1**

**Clock c2**

**Clock res**

Sequence s1 : IntegerSequence =

un = 1;

six = 6

**Expression** myDefer = **Defer**( BaseClock -> **c1**, DelayClock -> **c2**, DelayPatternExpression -> s1)

** Relation** r1[**Coincides**](Clock1 -> **c3**, Clock2 -> c1wait5 )

}

}

Simulation results:

The defer expression that causes the death simulation is represented on the next picture. The implicit clock dies after its last tick. Because res coincides with the implicit clock, then it dies at the same time than the implicit clock.