Selection
- Charles André, Frédéric Mallet, Robert de Simone: Modeling Time(s). MoDELS: 559-573 (2007). bib
First Presentation of MARTE Time Model and the use of Logical Clocks within a UML Profile.
- Charles André: Syntax and Semantics of the Clock Constraint Specification Language (CCSL). RR-6925, INRIA (2009)
First Comprehensive Release of the operational semantics of CCSL. Superseded by RR-8628.
- Julien DeAntoni, Frédéric Mallet: TimeSquare: Treat Your Models with Logical Time. TOOLS (50): 34-41 (2012). bib
First Introduction to TimeSquare Features.
- Julien DeAntoni, Charles André, Régis Gascon: CCSL Denotational Semantics. RR-8628, INRIA (2014).
- Julien Deantoni, Papa Issa Diallo, Joël Champeau, Benoit Combemale, Ciprian Teodorov. Operational Semantics of the Model of Concurrency and Communication Language. [Research Report] RR-8584, INRIA. 2014, pp.23. 〈hal-01060601v2〉
- Frédéric Mallet, Robert de Simone: Correctness issues on MARTE/CCSL constraints. Sci. Comput. Program. 106: 78-92 (2015). bib
Verification issues with CCSL and survey of attempts for exhaustive verification of CCSL.
Applications and extensions
- Mathieu Montin, Marc Pantel: Ordering Strict Partial Orders to Model Behavioral Refinement, EPTCS 282, Logic in Computer Science, 23-38, 2018.
- Bo Chen, Xi Li, Xuehai Zhou: Model checking of MARTE/CCSL time behaviors using timed I/O automata, Journal of Systems Architecture, 88:120-125, August, Elsevier, 2018.
- Eun-Young Kang, Dongrui Mu, Li Huang: Probabilistic Verification of Timing Constraints in Automotive Systems Using UPPAAL-SMC. IFM 2018: 236-254. bib
-
Hai Nguyen Van, Thibaut Balabonski, Frédéric Boulanger, Chantal Keller, Benoît Valiron, Burkhart Wolff: A Symbolic Operational Semantics for TESL – With an Application to Heterogeneous System Testing. FORMATS 2017: 318-334. bib
-
Min Zhang, Yunhui Ying: Towards SMT-based LTL model checking of clock constraint specification language for real-time and embedded systems. LCTES 2017: 61-70. bib
-
Cristina Seceleanu, Morgan E. Johansson, Jagadish Suryadevara, Gaetana Sapienza, Tiberiu Seceleanu, Stein Erik Ellevseth, Paul Pettersson: Analyzing a wind turbine system: From simulation to formal verification. Sci. Comput. Program. 133: 216-242 (2017). bib
-
Xiaohong Chen, Ling Yin, Yijun Yu, Zhi Jin: Transforming Timing Requirements into CCSL Constraints to Verify Cyber-Physical Systems. ICFEM 2017: 54-70. bib
-
Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler: Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models. MEMOCODE 2016: 78-84. bib
-
Aamir M. Khan, Muhammad Rashid: Generation of SystemVerilog Observers from SysML and MARTE/CCSL. ISORC 2016: 61-68. bib
-
Yanwen Chen, Yixiang Chen, Eric Madelaine: Timed-pNets: a communication behavioural semantic model for distributed systems. Frontiers Comput. Sci. 9(1): 87-110 (2015). bib
-
Judith Peters: Exploiting MARTE/CCSL in modern design flows. PhD Thesis. University of Bremen, Germany 2015, pp. 1-116. bib
-
Lulu Yao, Jing Liu, Yan Zhang, Yuejun Wang, Haiying Sun, Qingsheng Wang, Dehui Du, Xiaohong Chen: HSD: Hybrid MARTE Sequence Diagram. QRS 2015: 189-194. bib
-
Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler: A generic representation of CCSL time constraints for UML/MARTE models. DAC 2015: 122:1-122:6. bib
-
Judith Peters, Rolf Drechsler: Analyzing and Simulating Time Descriptions from UML/MARTE CCSL. SyDe Summer School 2015: 293-295. bib
-
Eun-Young Kang, Pierre-Yves Schobbens: Schedulability analysis support for automotive systems: from requirement to implementation. SAC 2014: 1080-1085. bib
-
Ning Ge: Property driven verification framework: application to real time property for UML MARTE software design. PhD Thesis. National Polytechnic Institute of Toulouse, France 2014. bib
-
Judith Peters, Robert Wille, Rolf Drechsler: Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL. ICECCS 2014: 116-125. bib
-
Jagadish Suryadevara: Validating EAST-ADL Timing Constraints Using UPPAAL. EUROMICRO-SEAA 2013: 268-275. bib
-
Huafeng Yu, Jean-Pierre Talpin, Loïc Besnard, Thierry Gautier, Hervé Marchand, Paul Le Guernic: Polychronous controller synthesis from MARTE CCSL timing specifications. MEMOCODE 2011: 21-30. bib
- Frédéric Boulanger, Ayman Dogui, Cécile Hardebolle, Christophe Jacquet, Dominique Marcadet, Iuliana Prodan: Semantic Adaptation using CCSL Clock Constraints. ECEASST 50 (2011). bib
